Digital IP Verification Engineer @ NXP Munich · previously PlanV · TUM M.Sc.
Verilator org member · 160+ merged PRs in Verilator · UVM on open-source simulators · AI for verification
- 🚀 160+ merged pull requests in Verilator: constrained randomization, SVA and UVM-related features. Member of the Verilator GitHub organization.
- 🧪 Industrial UVM on an open-source simulator: OpenHW's cv32e40p UVM testbench (core-v-verif) running natively on Verilator, 0 UVM_FATAL / 0 UVM_ERROR.
- 🤖 Agentic AI development loop: 82 merged PRs in three months, human review on every patch.
- 🎓 2017–2021: B.Eng. EE @ HIT (Fuxin 🚄 Harbin)
- 🎓 2021–2024: M.Sc. EE @ TUM (China
✈️ Munich) - 🧪 Internships: Neusoft & Infineon (master thesis at Infineon)
- 💼 2024–2026: Verification Engineer @ PlanV
- 💼 2026–now: Digital IP Verification Engineer @ NXP
- 🎤 AI on Open-Source EDA: Closing the UVM-on-Verilator Gap with an Agentic Development Loop, DVCon Europe 2026 · Munich, Nov 17–18, 2026
- 📄 Enabling Industrial-Grade RISC-V UVM Verification on an Open-Source Simulator, Euromicro DSD 2026 (MATTERV) · Kraków, Sep 2026
- 📄 Advancing Open-Source Verification: Enabling Full Randomization in Verilator, DVCon Europe 2025
- 📄 Enable Reuse of SystemVerilog Verification IPs in cocotb/pyuvm, DVCon Europe 2024 (with Thorsten Dworzak and Johannes Grinschgl)
- #1 · 2024.08 · UVM in Verilator: Constraint random if/else
- #2 · 2024.10 · UVM in Verilator: CI system and test models
- #3 · 2024.11 · UVM in Verilator: Aggregate data type randomization
- #4 · 2025.02 · UVM in Verilator: Array constrained randomization
- #5 · 2025.07 · UVM in Verilator: Struct constrained randomization
- #6 · 2026.02 · 🤖 Verilator Gap Checker with AI
- #7 · 2026.06 · 🤖 Verilator Developer: an AI-native pipeline for Verilator contributions
- 🧰 Toy4Joy_DV: DV playground for SV / UVM / Verilator / cocotb, with practical examples for onboarding and quick experiments.
- 📘 cocotb-BSHL: my master thesis work at Infineon, giving cocotb/pyuvm access to SystemVerilog verification IP.
- 🧪 PlanV_Verilator_Feature_Tests: the CI flow we used at PlanV to validate Verilator features.
- Email: wangyilou123@gmail.com
Open-source work shown here was done during my time at PlanV and before. Views are my own.