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1. spi-fpga-core spi-fpga-core Public

   SPI master + slave IP core in SystemVerilog: all 4 modes, FIFOs, multi-CS, AXI4-Lite wrapper. Tested with cocotb, SymbiYosys formal proofs and CI.

   Python 4

2. keccak-fpga-core keccak-fpga-core Public

   Keccak/SHA-3 family IP core in SystemVerilog. FIPS-202 + Ethereum Keccak-256 compliant, dual-licensed.

   SystemVerilog 2

3. aes128-fpga-core aes128-fpga-core Public

   AES-128 IP core in SystemVerilog. FIPS-197 compliant, dual-licensed, with secure (DPA-resistant) and pipelined variants.

   C++ 1

4. sha256-fpga-core sha256-fpga-core Public

   SHA-256 + HMAC-SHA-256 hash IP cores in SystemVerilog. FIPS-180-4 + RFC 4231 compliant.

   C++ 1

5. axi4lite-slave-fpga-core axi4lite-slave-fpga-core Public

   AXI4-Lite slave parametrizable IP core in SystemVerilog. ARM AMBA AXI compliant, with YAML to SV+C register-map generator.

   SystemVerilog 1

6. aes-xts-fpga-core aes-xts-fpga-core Public

   AES-XTS-128 IP core in SystemVerilog. IEEE 1619 compliant for full-disk encryption (BitLocker/FileVault/LUKS).

   SystemVerilog 1