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64bitandstuff - #340
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64bitandstuff#340
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Also fold physical addresses to the board's 32 decoded bits The IP28 flooded "MC: CPU Error at 20404000" and stopped in early kernel start once translation kept the whole physical address. IRIX's page-table entries keep software bits (the PFN lock among them) just above the PFN, so they reach EntryLo and come out as physical bits 32 and up: the kernel stack's wired entry has PFN 0x620404. The MC decodes 32 bits and the board aliases the rest away; the old u32 address modelled that by accident. MipsExecutor::phys_mask is the board's decode width, applied after phys_alias to mapped, xkphys and ERL-identity translations. The Indy, Indigo2 and O2 set it to 32 bits; the default folds nothing. Folding in the CPU keeps the caches, the ppmem window and the nutlb on the same addresses as before. MC error reports print the full address (the register keeps 32 bits), and tools/mon.py takes IRIS_MON_PORT for an iris on another port. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
A headless O2 reported CRIME revision 0x11 and MACE revision 1, because both were set only when the PS/2 keyboard was attached. Every O2 has its GBE and the same chips, so CRIME now always reads 0xa1 and MACE always revision 2; headless only leaves the PS/2 ports empty. IRIX 6.5.22 still panics early on a headless O2 (a NULL dereference that the nested refill reports as a fault at 0xff800000); recorded as open in clanker/devices/ip32-headless-irix-panics.md. The graphics console boots. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
PciDma::dma_read/dma_write take a u64 PCI bus address, for masters that use dual address cycles, and return PciDmaStatus (Ok or MasterAbort) instead of a bool. MACE's HostMemory and the AIC-7880 follow; a 64-bit bus address is no longer folded into the low 4 GB. No change for the O2, which still hands every function one shared HostMemory. clanker/plans/pci-dma-port.md is the plan this starts: the trait shared on the O2 and handed out per device by the Octane's Bridge, whose DMA translation depends on the mastering device. It records the Bridge and Xbridge facts the design rests on (DMA regions, Device(x), ATEs, PIO windows, interrupt pins, byte swap) and the remaining steps. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
IRIX 6.5.22 panicked in early console setup (TLBMISS: KERNEL FAULT at 0xff800000) on a headless O2 and with less than 1 GB of memory. The fault is crmFifoWait, called from crimeInitHW during cn_init: it waits for the rendering engine's interface buffer to empty for about 4096 us_delay(1) polls of the status word, and on timeout reports through a structure that does not exist yet. The engine runs on its own host thread and was still working through a startup queue when the guest's microseconds ran out. A read of the status word while the engine is busy now gives it up to 100 us of host time before answering. Boots to login with 32, 64, 128, 256, 224, 384 and 512 MB and 1 GB, and headless. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
IRIX now boots with any O2 memory fit from a single 32 MB kit to 1 GB. NetBSD 11's 32-bit IP3x kernel uses only the first 256 MB whatever is fitted (checked with 256 MB, 512 MB and 1 GB: "total memory = 255 MB" each time, installer up in all three). MEM_BANK_CTRL1 said 0x218; CRIME's bank controls are at 0x208 + 8 * n, which every user computes from MEM_BANK_CTRL0. It was unused. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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make bus trait 64 bit fix #338
clean up o2 dma/pci memory access paths
fix o2 memory configs and bank sizes