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feat(riscv): add plic and interrupt controller - #735
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@ytakano done! |
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Description
This PR adds a PLIC driver for RISC-V, as well as a first implementation of the
InterruptControllertrait. It does not register it in the kernel. I plan to include this functionality later, once I can test everything on QEMU.Interrupt numbers
Interrupt ID 0 corresponds to CLINT's software interrupt. The rest of the interrupts correspond to PLIC's external interrupts.
External interrupts are triggered by external events (e.g., GPIO or I2C). Thus, they cannot be used for IPI.
The PLIC driver expects an
extern "Rust" fn __awkernel_plic_clear_ext_interrupt(irq: u16) → Result<(), plic::Error>function.This function is platform-dependent, so we use the weak linkage trick.
The default implementation returns
Err(Error::NotImplemented), but BSPs are expected to override them.This function must interact with the appropriate peripheral to clear the external interrupt. Otherwise, the PLIC will be continuously triggering the pending interrupt.
Related links
This PR is inspired by the work in #676. However, it contains less changes so it is easier to review. Future PRs will gradually include all the required parts.
How was this PR tested?
scripts/ci.shpasses on my machine.